Low Power Reconfigurable Analog-to-Digital Converter

The objective of this project is to create a low power A/D converter␣ to be employed in a battery power ed wireless sensor. The key requirement of the converter is that it be able to cater to a wide␣ range of input data-rate (1sample/ s to >1Msample/s), and produce a␣ r esolution ranging from 8 bits to as high as 16bits, consuming the lowest possible power consumption. A possible subset of applications envisioned for the A/D converter is depicted in Figure 2. This large size of data-rate versus resolution space warrants the need for several different A/D converter architectures. However, such a converter implementation would require a prohibitively large area. Further, in the event that the total area required is larger than that can be supported by a single chip, the speed of the␣ converter would be dramatically r educed due to offchip parasitic capacitance.